Method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry

ABSTRACT

Enhanced Electrochemical fabrication processes are provided that can form three-dimensional multi-layer structures using semiconductor based circuitry as a substrate. Electrically functional portions of the structure are formed from structural material (e.g. nickel) that adheres to contact pads of the circuit. Aluminum contact pads and silicon structures are protected from copper diffusion damage by application of appropriate barrier layers. In some embodiments, nickel is applied to the aluminum contact pads via solder bump formation techniques using electroless nickel plating. In other embodiments, selective electroless copper plating or direct metallization is used to plate sacrificial material directly onto dielectric passivation layers. In still other embodiments, structural material deposition locations are shielded, then sacrificial material is deposited, the shielding is removed, and then structural material is deposited. In still other embodiments structural material is made to attached to non-contact pad regions.

RELATED APPLICATIONS

[0001] This application claims benefit of U.S. Provisional PatentApplication No. 60/379,133, filed on May 7, 2002 which is herebyincorporated herein by reference as if set forth in full.

FIELD OF THE INVENTION

[0002] This invention relates to the field of electrochemical depositionand more particularly to the field of electrochemical fabrication whichincludes electrochemical deposition of one or more materials accordingto desired cross-sectional configurations so as to build upthree-dimensional structures from a plurality of at least partiallyadhered layers of deposited material. More particularly the inventionrelates to the integration of multilayer electrochemically fabricatedstructures with semiconductor circuitry and in particular to theformation of such structures on integrated circuits.

BACKGROUND

[0003] A technique for forming three-dimensional structures (e.g. parts,components, devices, and the like) from a plurality of adhered layerswas invented by Adam L. Cohen and is known as ElectrochemicalFabrication. It is being commercially pursued by MEMGen® Corporation ofBurbank, Calif. under the name EFAB™. This technique was described inU.S. Pat. No. 6,027,630, issued on Feb. 22, 2000. This electrochemicaldeposition technique allows the selective deposition of a material usinga unique masking technique that involves the use of a mask that includespatterned conformable material on a support structure that isindependent of the substrate onto which plating will occur. Whendesiring to perform an electrodeposition using the mask, the conformableportion of the mask is brought into contact with a substrate while inthe presence of a plating solution such that the contact of theconformable portion of the mask to the substrate inhibits deposition atselected locations. For convenience, these masks might be genericallycalled conformable contact masks; the masking technique may begenerically called a conformable contact mask plating process. Morespecifically, in the terminology of MEMGen® Corporation of Burbank,Calif. such masks have come to be known as INSTANT MASKS™ and theprocess known as INSTANT MASKING™ or INSTANT MASK™ plating. Selectivedepositions using conformable contact mask plating may be used to formsingle layers of material or may be used to form multi-layer structures.The teachings of the '630 patent are hereby incorporated herein byreference as if set forth in full herein. Since the filing of the patentapplication that led to the above noted patent, various papers aboutconformable contact mask plating (i.e. INSTANT MASKING) andelectrochemical fabrication have been published:

[0004] 1. A. Cohen, G. Zhang, F. Tseng, F. Mansfeld, U. Frodis and P.Will, “EFAB: Batch production of functional, fully-dense metal partswith micro-scale features”, Proc. 9th Solid Freeform Fabrication, TheUniversity of Texas at Austin, p161, August 1998.

[0005] 2. A. Cohen, G. Zhang, F. Tseng, F. Mansfeld, U. Frodis and P.Will, “EFAB: Rapid, Low-Cost Desktop Micromachining of High Aspect RatioTrue 3-D MEMS”, Proc. 12th IEEE Micro Electro Mechanical SystemsWorkshop, IEEE, p244, January 1999.

[0006] 3. A. Cohen, “3-D Micromachining by Electrochemical Fabrication”,Micromachine Devices, March 1999.

[0007] 4. G. Zhang, A. Cohen, U. Frodis, F. Tseng, F. Mansfeld, and P.Will, “EFAB: Rapid Desktop Manufacturing of True 3-D Microstructures”,Proc. 2nd International Conference on Integrated MicroNanotechnology forSpace Applications, The Aerospace Co., April 1999.

[0008] 5. F. Tseng, U. Frodis, G. Zhang, A. Cohen, F. Mansfeld, and P.Will, “EFAB: High Aspect Ratio, Arbitrary 3-D Metal Microstructuresusing a Low-Cost Automated Batch Process”, 3rd International Workshop onHigh Aspect Ratio MicroStructure Technology (HARMST'99), June 1999.

[0009] 6. A. Cohen, U. Frodis, F. Tseng, G. Zhang, F. Mansfeld, and P.Will, “EFAB: Low-Cost, Automated Electrochemical Batch Fabrication ofArbitrary 3-D Microstructures”, Micromachining and MicrofabricationProcess Technology, SPIE 1999 Symposium on Micromachining andMicrofabrication, September 1999.

[0010] 7. F. Tseng, G. Zhang, U. Frodis, A. Cohen, F. Mansfeld, and P.Will, “EFAB: High Aspect Ratio, Arbitrary 3-D Metal Microstructuresusing a Low-Cost Automated Batch Process”, MEMS Symposium, ASME 1999International Mechanical Engineering Congress and Exposition, November,1999.

[0011] 8. A. Cohen, “Electrochemical Fabrication (EFABTM)”, Chapter 19of The MEMS Handbook, edited by Mohamed Gad-El-Hak, CRC Press, 2002.

[0012] 9. “Microfabrication—Rapid Prototyping's Killer Application”,pages 1-5 of the Rapid Prototyping Report, CAD/CAM Publishing, Inc.,June 1999.

[0013] The disclosures of these nine publications are herebyincorporated herein by reference as if set forth in full herein.

[0014] The electrochemical deposition process may be carried out in anumber of different ways as set forth in the above patent andpublications. In one form, this process involves the execution of threeseparate operations during the formation of each layer of the structurethat is to be formed:

[0015] 1. Selectively depositing at least one material byelectrodeposition upon one or more desired regions of a substrate.

[0016] 2. Then, blanket depositing at least one additional material byelectrodeposition so that the additional deposit covers both the regionsthat were previously selectively deposited onto, and the regions of thesubstrate that did not receive any previously applied selectivedepositions.

[0017] 3. Finally, planarizing the materials deposited during the firstand second operations to produce a smoothed surface of a first layer ofdesired thickness having at least one region containing the at least onematerial and at least one region containing at least the one additionalmaterial.

[0018] After formation of the first layer, one or more additional layersmay be formed adjacent to the immediately preceding layer and adhered tothe smoothed surface of that preceding layer. These additional layersare formed by repeating the first through third operations one or moretimes wherein the formation of each subsequent layer treats thepreviously formed layers and the initial substrate as a new andthickening substrate.

[0019] Once the formation of all layers has been completed, at least aportion of at least one of the materials deposited is generally removedby an etching process to expose or release the three-dimensionalstructure that was intended to be formed.

[0020] The preferred method of performing the selectiveelectrodeposition involved in the first operation is by conformablecontact mask plating. In this type of plating, one or more conformablecontact (CC) masks are first formed. The CC masks include a supportstructure onto which a patterned conformable dielectric material isadhered or formed. The conformable material for each mask is shaped inaccordance with a particular cross-section of material to be plated. Atleast one CC mask is needed for each unique cross-sectional pattern thatis to be plated.

[0021] The support for a CC mask is typically a plate-like structureformed of a metal that is to be selectively electroplated and from whichmaterial to be plated will be dissolved. In this typical approach, thesupport will act as an anode in an electroplating process. In analternative approach, the support may instead be a porous or otherwiseperforated material through which deposition material will pass duringan electroplating operation on its way from a distal anode to adeposition surface. In either approach, it is possible for CC masks toshare a common support, i.e. the patterns of conformable dielectricmaterial for plating multiple layers of material may be located indifferent areas of a single support structure. When a single supportstructure contains multiple plating patterns, the entire structure isreferred to as the CC mask while the individual plating masks may bereferred to as “submasks”. In the present application such a distinctionwill be made only when relevant to a specific point being made.

[0022] In preparation for performing the selective deposition of thefirst operation, the conformable portion of the CC mask is placed inregistration with and pressed against a selected portion of thesubstrate (or onto a previously formed layer or onto a previouslydeposited portion of a layer) on which deposition is to occur. Thepressing together of the CC mask and substrate occur in such a way thatall openings, in the conformable portions of the CC mask contain platingsolution. The conformable material of the CC mask that contacts thesubstrate acts as a barrier to electrodeposition while the openings inthe CC mask that are filled with electroplating solution act as pathwaysfor transferring material from an anode (e.g. the CC mask support) tothe non-contacted portions of the substrate (which act as a cathodeduring the plating operation) when an appropriate potential and/orcurrent are supplied.

[0023] An example of a CC mask and CC mask plating are shown in FIGS.1(a)-1(c). FIG. 1(a) shows a side view of a CC mask 8 consisting of aconformable or deformable (e.g. elastomeric) insulator 10 patterned onan anode 12. The anode has two functions. FIG. 1(a) also depicts asubstrate 6 separated from mask 8. One is as a supporting material forthe patterned insulator 10 to maintain its integrity and alignment sincethe pattern may be topologically complex (e.g., involving isolated“islands” of insulator material). The other function is as an anode forthe electroplating operation. CC mask plating selectively depositsmaterial 22 onto a substrate 6 by simply pressing the insulator againstthe substrate then electrodepositing material through apertures 26 a and26 b in the insulator as shown in FIG. 1(b). After deposition, the CCmask is separated, preferably non-destructively, from the substrate 6 asshown in FIG. 1(c). The CC mask plating process is distinct from a“through-mask” plating process in that in a through-mask plating processthe separation of the masking material from the substrate would occurdestructively. As with through-mask plating, CC mask plating depositsmaterial selectively and simultaneously over the entire layer. Theplated region may consist of one or more isolated plating regions wherethese isolated plating regions may belong to a single structure that isbeing formed or may belong to multiple structures that are being formedsimultaneously. In CC mask plating as individual masks are notintentionally destroyed in the removal process, they may be usable inmultiple plating operations.

[0024] Another example of a CC mask and CC mask plating is shown inFIGS. 1(d)-1(f). FIG. 1(d) shows an anode 12′ separated from a mask 8′that comprises a patterned conformable material 10′ and a supportstructure 20. FIG. 1(d) also depicts substrate 6 separated from the mask8′. FIG. 1(e) illustrates the mask 8′ being brought into contact withthe substrate 6. FIG. 1(f) illustrates the deposit 22′ that results fromconducting a current from the anode 12′ to the substrate 6. FIG. 1(g)illustrates the deposit 22′ on substrate 6 after separation from mask8′. In this example, an appropriate electrolyte is located between thesubstrate 6 and the anode 12′ and a current of ions coming from one orboth of the solution and the anode are conducted through the opening inthe mask to the substrate where material is deposited. This type of maskmay be referred to as an anodeless INSTANT MASK™ (AIM) or as ananodeless conformable contact (ACC) mask.

[0025] Unlike through-mask plating, CC mask plating allows CC masks tobe formed completely separate from the fabrication of the substrate onwhich plating is to occur (e.g. separate from a three-dimensional (3D)structure that is being formed). CC masks may be formed in a variety ofways, for example, a photolithographic process may be used. All maskscan be generated simultaneously, prior to structure fabrication ratherthan during it. This separation makes possible a simple, low-cost,automated, self-contained, and internally-clean “desktop factory” thatcan be installed almost anywhere to fabricate 3D structures, leaving anyrequired clean room processes, such as photolithography to be performedby service bureaus or the like.

[0026] An example of the electrochemical fabrication process discussedabove is illustrated in FIGS. 2(a)-2(f). These figures show that theprocess involves deposition of a first material 2 which is a sacrificialmaterial and a second material 4 which is a structural material. The CCmask 8, in this example, includes a patterned conformable material (e.g.an elastomeric dielectric material) 10 and a support 12 which is madefrom deposition material 2. The conformal portion of the CC mask ispressed against substrate 6 with a plating solution 14 located withinthe openings 16 in the conformable material 10. An electric current,from power supply 18, is then passed through the plating solution 14 via(a) support 12 which doubles as an anode and (b) substrate 6 whichdoubles as a cathode. FIG. 2(a), illustrates that the passing of currentcauses material 2 within the plating solution and material 2 from theanode 12 to be selectively transferred to and plated on the cathode 6.After electroplating the first deposition material 2 onto the substrate6 using CC mask 8, the CC mask 8 is removed as shown in FIG. 2(b). FIG.2(c) depicts the second deposition material 4 as having beenblanket-deposited (i.e. non-selectively deposited) over the previouslydeposited first deposition material 2 as well as over the other portionsof the substrate 6. The blanket deposition occurs by electroplating froman anode (not shown), composed of the second material, through anappropriate plating solution (not shown), and to the cathode/substrate6. The entire two-material layer is then planarized to achieve precisethickness and flatness as shown in FIG. 2(d). After repetition of thisprocess for all layers, the multi-layer structure 20 formed of thesecond material 4 (i.e. structural material) is embedded in firstmaterial 2 (i.e. sacrificial material) as shown in FIG. 2(e). Theembedded structure is etched to yield the desired device, i.e. structure20, as shown in FIG. 2(f).

[0027] Various components of an exemplary manual electrochemicalfabrication system 32 are shown in FIGS. 3(a)-3(c). The system 32consists of several subsystems 34, 36, 38, and 40. The substrate holdingsubsystem 34 is depicted in the upper portions of each of FIGS. 3(a) to3(c) and includes several components: (1) a carrier 48, (2) a metalsubstrate 6 onto which the layers are deposited, and (3) a linear slide42 capable of moving the substrate 6 up and down relative to the carrier48 in response to drive force from actuator 44. Subsystem 34 alsoincludes an indicator 46 for measuring differences in vertical positionof the substrate which may be used in setting or determining layerthicknesses and/or deposition thicknesses. The subsystem 34 furtherincludes feet 68 for carrier 48 which can be precisely mounted onsubsystem 36.

[0028] The CC mask subsystem 36 shown in the lower portion of FIG. 3(a)includes several components: (1) a CC mask 8 that is actually made up ofa number of CC masks (i.e. submasks) that share a common support/anode12, (2) precision X-stage 54, (3) precision Y-stage 56, (4) frame 72 onwhich the feet 68 of subsystem 34 can mount, and (5) a tank 58 forcontaining the electrolyte 16. Subsystems 34 and 36 also includeappropriate electrical connections (not shown) for connecting to anappropriate power source for driving the CC masking process.

[0029] The blanket deposition subsystem 38 is shown in the lower portionof FIG. 3(b) and includes several components: (1) an anode 62, (2) anelectrolyte tank 64 for holding plating solution 66, and (3) frame 74 onwhich the feet 68 of subsystem 34 may sit. Subsystem 38 also includesappropriate electrical connections (not shown) for connecting the anodeto an appropriate power supply for driving the blanket depositionprocess.

[0030] The planarization subsystem 40 is shown in the lower portion ofFIG. 3(c) and includes a lapping plate 52 and associated motion andcontrol systems (not shown) for planarizing the depositions.

[0031] In addition to the above teachings, the '630 patent sets forth aprocess for integrating EFAB production with integrated circuits. Inthis process the structural EFAB material is plated onto and inelectrical contact with aluminum contact pads on the integrated circuit.These contact pads may be considered primary contact pads and thelocations to which contact with the EFAB structural material will bemade. In the described process the integrated circuit design is modifiedto include secondary contact pads (i.e. one or more pads) that areelectrically connected to the primary pads but are spaced therefrom by adistance. The secondary contact pads provide connection points forfeeding current to the primary contact pads so that the primary pads mayfunction as cathodes during electroplating operations. The process isillustrated in FIGS. 13a-13 i of that patent and is outlined as follows:

[0032] 1. The process starts with

[0033] a. An integrated circuit that includes a silicon wafer 38, aprimary contact pad 40, and a secondary contact pad 41 connected to theprimary pad by conductor 42. With the exception of the contact pads 40and 41 the integrated circuit is covered by passivation layer 44 (FIGS.13a & 13 b); and

[0034] b. A polyimide 34 coated copper disk 36. The polyimide may becoated onto the disk by spin coating.

[0035] 2. The copper disk 36 is adhered to the bottom surface of thesilicon wafer 38 with the polyimide 34 coated surface of the copper disklocated between the copper and the silicon.

[0036] 3. The silicon wafer is partially sawed through which assists inseparation of the die after processing.

[0037] 4. A photosensitive polyimide 35 is spin coated onto the topsurface of wafer 38. This coating provides an additional passivationlayer and potentially protects aluminum pads 40 and 41 during subsequentetching operations and it fills saw line 46.

[0038] 5. The polyimide 35 is patterned by selective exposure to lightand subsequent development to expose contact pads 40 and 41.

[0039] 6. The wafer is degreased and immersed in zincate platingsolution which provides a thin coating over the exposed aluminum contactpads to increase adhesion of subsequently deposited material.

[0040] 7. A photoresist is applied and patterned leaving a valley intowhich copper may be deposited to form a bus 48 that connects contactpads 41 (FIG. 13d). Copper is deposited, for example by sputtering andthe photoresist is removed leaving behind copper bus 48.

[0041] 8. A photoresist is applied and patterned to cover most of bus 48to prevent nickel from depositing thereon.

[0042] 9. Electrical contact is made with the portion of the bus 48 thatis not covered by photoresist and then plating enough nickel 50 (FIG.13e) on aluminum pad 40 to allow subsequent planarization

[0043] 10. The photoresist is removed thereby exposing the entire copperbus 48.

[0044] 11. A thin plating base of copper 51 is deposited, e.g. bysputtering, over the entire surface of the integrated circuit.

[0045] 12. Electrical contact is made with the copper and a sufficientamount of copper 52 is then electroplated over the entire wafer surfaceto allow planarization (FIG. 13F).

[0046] 13. The surface is planarized to expose the nickel 50 (FIG. 13g).

[0047] 14. Layers of the microstructure are electroplated (FIG. 13h).

[0048] 15. The copper deposited by electroplating and sputtering isremoved by etching.

[0049] 16. The polyimide 35 is stripped thereby exposing the resultingmicrostructure device 54 attached to wafer 38 (FIG. 13i).

[0050] Another method for forming microstructures from electroplatedmetals (i.e. using electrochemical fabrication techniques) is taught inU.S. Pat. No. 5,190,637 to Henry Guckel, entitled “Formation ofMicrostructures by Multiple Level Deep X-ray Lithography withSacrificial Metal layers. This patent teaches the formation of metalstructure utilizing mask exposures. A first layer of a primary metal iselectroplated onto an exposed plating base to fill a void in aphotoresist, the photoresist is then removed and a secondary metal iselectroplated over the first layer and over the plating base. Theexposed surface of the secondary metal is then machined down to a heightwhich exposes the first metal to produce a flat uniform surfaceextending across the both the primary and secondary metals. Formation ofa second layer may then begin by applying a photoresist layer over thefirst layer and then repeating the process used to produce the firstlayer. The process is then repeated until the entire structure is formedand the secondary metal is removed by etching. The photoresist is formedover the plating base or previous layer by casting and the voids in thephotoresist are formed by exposure of the photoresist through apatterned mask via X-rays or UV radiation.

[0051] Even in view of these teachings a need remains in theelectrochemical fabrication arts for alternative processes and simplerprocesses for integrating electrochemically fabricated structures withintegrated circuits and particularly for processes that allow formationof multilayer electrochemically fabricated structures on and inelectrical contact with semiconductor produced circuitry.

SUMMARY OF THE INVENTION

[0052] It is an object of some embodiments of various aspects of thepresent invention to provide alternative processes for integratingelectrochemically fabricated multilayer structures with integratedcircuits.

[0053] It is an object of some embodiments of various aspects of thepresent invention to provide simpler processes for integratingelectrochemically fabricated multilayer structures with integratedcircuits.

[0054] It is an object of some embodiments of various aspects of thepresent invention to provide simpler processes that allow formation ofmultilayer electrochemically fabricated structures on and in electricalcontact with semiconductor produced circuitry.

[0055] Other objects and advantages of various aspects of the inventionwill be apparent to those of skill in the art upon review of theteachings herein. The various aspects of the invention, set forthexplicitly herein or otherwise ascertained from the teachings herein,may address any one of the above objects alone or in combination, oralternatively may not address any of the objects set forth above butinstead address some other object ascertained from the teachings herein.It is not intended that all of these objects be addressed by any singleaspect of the invention even though that may be the case with regard tosome aspects.

[0056] A first aspect of the invention provides an electrochemicalfabrication process for producing a three-dimensional structure from aplurality of adhered layers, the process including: (A) selectivelydepositing at least a portion of a layer onto the substrate, wherein thesubstrate may include previously deposited material; (B) forming aplurality of layers such that successive layers are formed adjacent toand adhered to previously deposited layers, wherein said formingincludes repeating operation (A) a plurality of times; wherein at leasta plurality of the selective depositing operations include: (1) locatinga mask on or in proximity to a substrate; (2) in presence of a platingsolution, conducting an electric current between an anode and thesubstrate through the at least one opening in the mask, such that aselected deposition material is deposited onto the substrate to form atleast a portion of a layer; and (3) separating the selected preformedmask from the substrate; wherein the substrate includes a semiconductorwafer or single die containing electrical circuitry and having contactpads to which structural material is to connect; and wherein the processof contacting the contact pads with structural material includestreating the wafer or die with a transition treatment and then applyinga structural material to the contact pads by application of anelectroless plating solution to the contact pads for a sufficient timeto form a deposition of desired thickness.

[0057] A second aspect of the invention provides an electrochemicalfabrication process for producing a three-dimensional structure from aplurality of adhered layers, the process including: (A) selectivelydepositing at least a portion of a layer onto the substrate, wherein thesubstrate may include previously deposited material; (B) forming aplurality of layers such that successive layers are formed adjacent toand adhered to previously deposited layers, wherein said formingincludes repeating operation (A) a plurality of times; wherein at leasta plurality of the selective depositing operations include: (1) locatinga mask on or in proximity to a substrate; (2) in presence of a platingsolution, conducting an electric current between an anode and thesubstrate through the at least one opening in the mask, such that aselected deposition material is deposited onto the substrate to form atleast a portion of a layer; and (3) separating the selected preformedmask from the substrate; wherein the substrate includes a semiconductorwafer or single die containing electrical circuitry and having contactpads to which structural material is to connect; and wherein the processof forming a conductive layer over a surface of the wafer or dieincludes: (a) shielding at least the contact pads with a shieldingmaterial; (b) depositing a sacrificial material to unshielded regionsusing at least one of direct metallization or direct plating orelectroless deposition; (c) removing the shielding after a deposition ofthe sacrificial material; and (d) depositing a structural material tothe contact pads.

[0058] A third aspect of the invention provides an electrochemicalfabrication process for producing a three-dimensional structure from aplurality of adhered layers, the process including: selectivelydepositing at least a portion of a layer onto the substrate, wherein thesubstrate may include previously deposited material; (A) forming aplurality of layers such that successive layers are formed adjacent toand adhered to previously deposited layers, wherein said formingincludes repeating operation (A) a plurality of times; wherein at leasta plurality of the selective depositing operations include: (1) locatinga mask on or in proximity to a substrate; (2) in presence of a platingsolution, conducting an electric current between an anode and thesubstrate through the at least one opening in the mask, such that aselected deposition material is deposited onto the substrate to form atleast a portion of a layer; and (3) separating the selected preformedmask from the substrate; wherein the substrate includes a semiconductorwafer or single die containing electrical circuitry and having contactpads to which structural material is to connect and having regions ofdielectric where structural material is to adhere; and wherein theprocess of contacting the structural material to regions of dielectricmaterial includes depositing a conductive base material, in a patternedor unpatterned formation, depositing structural material to at leastselected locations of the base material and, if base material exists inany regions which are not overlaid by structural material, subsequentlyremoving any such base material that is not overlaid.

[0059] Further aspects of the invention will be understood by those ofskill in the art upon reviewing the teachings herein. Other aspects ofthe invention may involve combinations of the above noted aspects of theinvention and/or addition of various features of one or moreembodiments. Other aspects of the invention may involve apparatus thatcan be used in implementing one or more of the above method aspects ofthe invention. These other aspects of the invention may provide variouscombinations of the aspects presented above as well as provide otherconfigurations, structures, functional relationships, and processes thathave not been specifically set forth above.

BRIEF DESCRIPTION OF THE DRAWINGS

[0060] FIGS. 1(a)-1(c) schematically depict side views of various stagesof a CC mask plating process, while FIGS. 1(d)-(g) schematically depicta side views of various stages of a CC mask plating process using adifferent type of CC mask.

[0061] FIGS. 2(a)-2(f) schematically depict side views of various stagesof an electrochemical fabrication process as applied to the formation ofa particular structure where a sacrificial material is selectivelydeposited while a structural material is blanket deposited.

[0062] FIGS. 3(a)-3(c) schematically depict side views of variousexample subassemblies that may be used in manually implementing theelectrochemical fabrication method depicted in FIGS. 2(a)-2(f).

[0063] FIGS. 4(a)-4(i) schematically depict the formation of a firstlayer of a structure using adhered mask plating where the blanketdeposition of a second material overlays both the openings betweendeposition locations of a first material and the first material itself.

[0064] FIGS. 5(a)-5(l) schematically depict side views of various stagesof a process according to a first embodiment for formingelectrochemically fabricated structures on integrated circuits.

[0065] FIGS. 6(a)-6(f) schematically depict side views of various stagesof a process according to one variation of a second embodiment forforming electrochemically fabricated structures on integrated circuits.

[0066] FIGS. 7(a)-7(h) schematically depict side views of various stagesof a process according to another variation of a second embodiment forforming electrochemically fabricated structures on integrated circuits.

[0067] FIGS. 8(a)-8(h) schematically depict side views of various stagesof a process according to another variation of a second embodiment forforming electrochemically fabricated structures on integrated circuits.

[0068] FIGS. 9(a)-9(i) schematically depict side views of various stagesof a process according to a third embodiment for formingelectrochemically fabricated structures on integrated circuits.

[0069] FIGS. 10(a)-10(i) schematically depict side views of variousstages of a process according to a fourth embodiment for formingelectrochemically fabricated structures on integrated circuits.

[0070] FIGS. 11(a)-11(k) schematically depict side views of variousstages of a process according to a fifth embodiment for formingelectrochemically fabricated structures on integrated circuits.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0071] FIGS. 1(a)-1(g), 2(a)-2(f), and 3(a)-3(c) illustrate variousfeatures of one form of electrochemical fabrication that are known.Other electrochemical fabrication techniques are set forth in the '630patent referenced above, in the various previously incorporatedpublications, in various other patents and patent applicationsincorporated herein by reference, still others may be derived fromcombinations of various approaches described in these publications,patents, and applications, or are otherwise known or ascertainable bythose of skill in the art from the teachings set forth herein. All ofthese techniques may be combined with those of the various embodimentsof various aspects of the invention to yield enhanced embodiments. Stillother embodiments may be derived from combinations of the variousembodiments explicitly set forth herein.

[0072] FIGS. 4(a)-4(i) illustrate various stages in the formation of asingle layer of a multi-layer fabrication process where a second metalis deposited on a first metal as well as in openings in the first metalwhere its deposition forms part of the layer. In FIG. 4(a), a side viewof a substrate 82 is shown, onto which patternable photoresist 84 iscast as shown in FIG. 4(b). In FIG. 4(c), a pattern of resist is shownthat results from the curing, exposing, and developing of the resist.The patterning of the photoresist 84 results in openings or apertures92(a)-92(c) extending from a surface 86 of the photoresist through thethickness of the photoresist to surface 88 of the substrate 82. In FIG.4(d), a metal 94 (e.g. nickel) is shown as having been electroplatedinto the openings 92(a)-92(c). In FIG. 4(e), the photoresist has beenremoved (i.e. chemically stripped) from the substrate to expose regionsof the substrate 82 which are not covered with the first metal 94. InFIG. 4(f), a second metal 96 (e.g., silver) is shown as having beenblanket electroplated over the entire exposed portions of the substrate82 (which is conductive) and over the first metal 94 (which is alsoconductive). FIG. 4(g) depicts the completed first layer of thestructure which has resulted from the planarization of the first andsecond metals down to a height that exposes the first metal and sets athickness for the first layer. In FIG. 4(h) the result of repeating theprocess steps shown in FIGS. 4(b)-4(g) several times to form amulti-layer structure are shown where each layer consists of twomaterials. For most applications, one of these materials is removed asshown in FIG. 4(i) to yield a desired 3-D structure 98 (e.g. componentor device).

[0073] The various electrochemical fabrication processes used in variousembodiments, alternatives, and techniques disclosed herein may haveapplication to conformable contact masks and masking operations,proximity masks and masking operations (i.e. operations that use masksthat at least partially selectively shield a substrate by theirproximity to the substrate even if contact is not made), non-conformablemasks and masking operations (i.e. masks and operations based on maskswhose contact surfaces are not significantly conformable), and adheredmasks and masking operations (masks and operations that use masks thatare adhered to a substrate onto which selective deposition or etching isto occur as opposed to only being contacted to it).

[0074] Various embodiments are directed to techniques for interfacing orintegrating the electrochemical fabrication of multi-layer threedimensional structures with semiconductor devices (e.g. integratedcircuits) or devices produced by semiconductor manufacturing techniques.In the various embodiments presented hereafter, the semiconductordevices are provided in wafer form or die form and are used assubstrates for the electrochemical fabrication build up process. Thesedevices may be supplied with a passivation layer of adequate thicknessalready applied or such layers may be thickened prior to beginning theintegration process.

[0075] An integration process of a first preferred embodiment isdepicted in FIGS. 5(a)-5(l). A wafer 102 (or single die) is receivedfrom a standard IC fabrication process as shown in FIG. 5(a). The waferincludes electronic circuitry (not shown) with interface contact pads104 and connected bus contact pads 106 exposed. The pads are connectedby runners 108 which travel under a passivation layer 112 which coversthe surface of the wafer 102. Pads 104 and runners 108 may have beenspecifically designed with the intent of integrating a device made byelectrochemical fabrication, or alternatively pre-designed pads andinterconnects that can serve as runners may be used. Other pads (notshown) may be located on wafer 102 for purposes of wire bonding, flipchip packaging, etc.

[0076] A photoresist layer 122 is applied to the upper surface of thewafer as shown in FIG. 5(b). The photoresist is patterned so that theinterface pads 104 remain covered with hardened photoresist 124 as shownin FIG. 5(c). These covered pads are the ones to which the multilayerelectrochemically fabricated structure will be interfaced.

[0077] A thin layer of copper 126 is deposited over the entire surfaceas shown in FIG. 5(d). The deposition of the copper may for exampleoccur via a physical vapor deposition process (e.g. evaporated orsputtered), via electroless copper plating, or via direct metallization(i.e. direct plating). As the adhesion between the copper and theexposed aluminum bus contact pads is not critical it may be unnecessaryto apply a coating of zincate to the surface prior to copper deposition.But a zincate coating can be applied if desired or found necessary.Furthermore, as the bus contact pads 106 are located some distance fromthe interface contact pads, some damage by the copper to the bus contactpads may be acceptable. If such damage is a concern or found to be aproblem a barrier layer can be applied prior to the copper deposition.The barrier layer can then be removed toward the end of the processafter removal of the copper.

[0078] Next, electrical contact is made to the thin copper coating 126and thick copper 128 is plated as shown in FIG. 5(e) with a sufficientdepth to allow planarization to occur.

[0079] Next the applied coatings of copper are planarized to expose theresist 124 overlaying the interface contact pads 104 as shown in FIG.5(f). The resist 124 is then removed as shown in FIG. 5(g).

[0080] Next, a transition/barrier layer 132 is deposited onto the waferas shown in FIG. 5(h). The transition/barrier layer may include one orboth of a coating of an adhesion promoter (such as zincate) and adiffusion barrier such as titanium nitride (TiN), tantalum (Ta), and/ortantalum Nitride (TaN).

[0081] Next, electrical contact is made to the barrier layer and anelectrochemical fabrication structural material 134 (e.g., Ni) is platedthickly as shown in FIG. 5(i).

[0082] The deposits are again planarized as shown FIG. 5(j) exposing thethickly plated copper 128, and removing the barrier layer 132 exceptnear where it bounds the remaining nickel deposit 134 near the interfacecontact pads 104.

[0083] After again making electrical contact with the deposited metal,the electrochemical fabrication process is performed to build up themultiple layers of the three dimensional structure. The multilayerdeposition process is shown as completed in FIG. 5(k). Theelectrochemical fabrication process may be performed in a variety ofmanners and may include a variety of operations, such as, for example,selective depositions, selective etchings, blanket depositions, blanketetchings, planarization operations, and the like. It may also includevarious cleaning, activation, passivation, and other treatmentoperations. The selection of operations and the ordering of theoperations may vary from build process to build process or even fromlayer-to-layer within a single build process. Any selective depositionoperations, selective etching operations, or selective treatmentoperations may make use of contact masks (e.g. of the conformable ornon-conformable type), proximity masks, and/or adhered masks.

[0084] Next, all of the deposited copper is removed by etching asindicated in FIG. 5(l). Only the structural material from theelectrochemical fabrication process is left behind along with thetransition/barrier layer and the wafer or (single die) materialdeposited between the nickel and interface contact pads 104 and coveringa portion of the sides of the nickel around the interface contact pads.In this way the structure produced by electrochemical fabrication ismechanically and electrically interfaced to the metallization of thewafer.

[0085] Various alternatives to this first embodiment are possible. Forexample, a diffusion barrier layer could be deposited prior to the thincopper deposit 126 but after formation of the patterned resist 124, itcould be removed by controlled etching as its surface area would belargely exposed compared to the amount of exposure that a coatingbetween the interface contact pads 104 and the electrochemicallyfabricated structure would have. Due to this differential in exposure,it is believed that controlled etching may be performed, after layerformation is complete and the sacrificial material has been removed, toremove the barrier/transition layer from non-contact regions of theelectrochemically fabricated structure without excessive damage to thecontact regions after layer formation.

[0086] In another alternative embodiment, a barrier layer could beapplied prior to the application of the photoresist thereby obviatingthe need for a potential barrier layer prior to thin copper depositionof FIG. 5(d) and prior to the structural material deposition of FIG.5(i). In this alternative the uncovered portion of the barrier layerwould be removed after the removal of the copper.

[0087] In other alternative embodiments an adhesion transition layer mayalso be formed at different stages of the process.

[0088] In another alternative embodiment the runner and bus pad wouldnot be needed. In this alternative, the interface pad is made largerthan the area intended for deposition of the structural material (e.g.Ni). In this alternative, the portion of the interface contact pad 104that is not covered by the structural material serves as the contact pad(rather than having a remote contact pad). However, since Almetallization used in the integrated circuit device may be attacked bythe Cu stripper, etching of the Cu surrounding the structural materialmay damage the pad near the structural material. Using the runner andremote contact pad avoids this problem. Also this alternative embodimentcould benefit from the previous alternative embodiment where thepre-photoresist application of a barrier layer would inhibit the attack.

[0089] A second group of embodiments may take an alternative approach tointerfacing the wafer 102 to the initial conductive deposits onto whichthe multiple layers of the structure will be formed. FIGS. 6(a)-6(f)show one variation of the second group of embodiments. FIG. 6(a) showswafer 102 which may be prepared for the interfacing process by, forexample, coating pads 140 with a material that facilitateselectrodeposition or enhances adhesion (e.g., zincate treatment foraluminum pads) or adding additional passivation or barrier layers toprotect wafer 102 from materials (e.g., sodium) which may be present inplating or etching baths. In FIG. 6(b), a catalyst 142 for anelectroless plating bath that is suitable for depositing the sacrificialmaterial has been applied to the surface of the IC passivation layer112. Catalyst 142 may be selectively located on the passivation layeraway from contact pads 140 so that sacrificial material will not beinadvertently deposited onto the contact pads. However, if catalyst 142coats only the perimeter of pads 140 this is acceptable and may bedesirable in some embodiments. Catalyst 142 may be selectively applied,for example, by contacting the protruding surface of passivation 112with a plate or stamp coated with a thin film of catalyst 142, or byselectively dispensing catalyst 142 (e.g. via an ink jet or an extrusionhead).

[0090] In FIG. 6(c), sacrificial material 144 has been deposited ontothe catalyzed surface, which is assumed to be confined to the topsurface of passivation 112. In FIG. 6(d) the deposit has been continueduntil material 144 ‘mushrooms’ out and makes contact with the perimeterof pads 140. Once such contact is made, pads 140 are in electricalcontact with one another and with material 144 and can beelectrodeposited with another material. In FIG. 6(e), structuralmaterial has been electrodeposited onto pads 140. Finally, in FIG. 6(f),sacrificial and structural materials have been planarized so as tocreate a relatively flat and smooth substrate—as in FIG. 5(j)—suitableas a starting layer for further electrochemical fabrication operationswhere the starting layer includes regions of sacrificial material (e.g.,copper) and regions of structural material (e.g., nickel). In otherwords, the starting layer includes a structural material in regions thatcontact the pads and are intended to be electrically active, while atemporary presence of copper is located in all other regions.

[0091] FIGS. 7(a)-7(h) show another embodiment of the second group ofembodiments. The initial operations (FIGS. 7(a)-7(c)) are identical toFIGS. 6(a)-6(c) already described. Again, if catalyst 142 coats theperimeter of pads 140, this may be acceptable. In FIG. 7(d), additionalsacrificial material 148 has been electrodeposited over sacrificialmaterial 144 already deposited by electroless deposition in FIG. 7(c),with material 144 serving as a seed layer. In FIG. 7(e) theelectrodeposition process is continued such that the electrodepositedmaterial ‘mushrooms’ out far enough to reach contact pads 140. Oncecontact has been established with pad 140, a relatively thin deposit 150of material 148 forms over the entire surface of pads 140. In FIG. 7(f),thin deposit 150 has been etched to re-expose pads 140. In FIG. 7(g),structural material 146 is deposited, and in FIG. 7(h), the twomaterials are planarized, with the wafer ready to receive the firstlayer in an electrochemical fabrication process.

[0092] It is possible that deposition of extra material 148 as performedby the operation that let to the state depicted in FIG. 7(d), will notoccur in some electrically isolated regions of material 144 (instead ispossible that material 146 will begin depositing there once depositionthickness of material on the pads reaches a level that contacts the edgeof material 144). This failure to deposit, or to deposit the wrongmaterial may be problematic in some embodiments depending on how andwhere material will be deposited in the formation of subsequent layers,requirement on electrical isolation, and/or on the planarization levelchosen when trimming this first integrating layer. As shown, in FIG.7(h) the plane of planarization passes through material 148 and is abovematerial 144 and thus if material 148 did not exist over some regions ofmaterial 144 an un-planar surface may result or if material 146 weredeposited there it would remain in the final structure. However, in somealternative embodiments, this problems may be avoided by making level ofplanarization lower such that it passes through material 144 and in suchalternatives the lack of material 148 or inadvertent existence ofmaterial 146 in some regions would not be problematic.

[0093] FIGS. 8(a)-8(h) show another embodiment of the second group ofembodiments. FIGS. 8(a)-8(d) shows processing identical to that of FIGS.6(a)-6(d), except that in FIG. 8(d), although material 144 has startedto ‘mushroom’ out, the deposit has not been continued long enough toallow material 144 to make contact with pads 140. If desired, material144 may be thickened by electrodepositing additional sacrificialmaterial on top of it. In FIG. 8(e), structural material 146 has beenelectrodeposited over electroless-deposited material 144 (except for anyregions of material 146 that might be electrically isolated). In FIG.8(f), the electrodeposition of structural material 146 has beencontinued long enough for the electrodeposited material to ‘mushroom’out far enough to touch the contact pads 140. Once this contact has beenestablished with pads 140, a layer of material 146 begins to cover theentire surface of pads 140 and this continues to grow in thickness, asshown in FIG. 8(g). Finally, FIG. 8(h) shows the result ofplanarization, with the wafer ready to receive the first layer in anelectrochemical fabrication process. In this embodiment, initial failureto deposit structural material 146 over some regions of material 144 isnot problematic since once plating to the pads begins and the depositionheight grows sufficiently to cause contact with any unplated sacrificialmaterial, deposition of structural material over entire region ofunplated sacrificial material will begin immediately.

[0094] In some alternative embodiments, over depositing sacrificialmaterial with structural material may be avoided or minimized by use ofmasking operations or other surface treatment operations such that thestructural material is essentially selectively deposited. After suchselective deposition of structural material, planarization may occur ifdesired or needed or a subsequent selective or blanket deposition ofsacrificial material may occur to increase its height prior to anyplanarization operation or prior initiating formation of a subsequentlayer of material. In some embodiments, where barrier layers or adhesionlayers are applied prior to the plating of structural material intopockets formed in sacrificial material, the mushrooming effect notedabove may not be necessary as the presence of the barrier or adhesionlayers may provided the required conductivity

[0095] In some alternative embodiments, the IC passivation layer may bethickened prior to performing electroless deposition of sacrificialmaterial, e.g., by coating with a patterned polyimide or photoresist.This thickening may be useful in limiting the spread of plated copperfrom the passivation layer over the edges of the passivation layer andonto the contact pads.

[0096] A one variation of a third group of embodiments, is exemplifiedin FIGS. 9(a)-9(i), and may use electroless nickel plating or othermethods commonly used to produce bumps on semiconductor wafers (e.g.,gold plating, ball bumping, stud bumping) to get an initial deposit ofthe structural material onto contact pads of an IC. The method assumesthat the material of the bumps, balls, or studs formed on the wafer iscompatible with and will not substantially be attacked by the etchantused to remove the sacrificial material from the electrochemicallyfabricated structure. An example of such an embodiment, assuming the useof electroless nickel bumping, includes the following operations

[0097] 1. Receive a wafer (or single die) from a standard IC fabricationprocess (FIG. 9(a)).

[0098] 2. Assuming all exposed contact pads are to be contact locationsfor electrochemical fabrication, an electroless nickel deposition isapplied to the contact pads (FIG. 9(b)) by a process along the lines ofthat being commercialized by Pac Tech GmbH which may include, forexample:

[0099] Cleaning wafer 102,

[0100] Applying a zincate treatment to the contact pads, for example by:

[0101] Placing the wafer into a zincate solution for less than about 3minutes and then rinsing in deionized water.

[0102] Repeating the placing and rinsing as necessary or desired.

[0103] Placing the wafer into a nickel solution such as 8-10% NiP at 85°C. for 12-15 minutes to form nickel bumps 152 of at least 5 μmthickness. The wafer may be left in longer to increase the thickness ofthe bumps which may make planarization easier in a subsequent operation.

[0104] After plating, rinse in DI water.

[0105] Normally, a gold coating 154 is applied over the nickel bump foroxidation resistance but this may be omitted.

[0106] If not all of the contact pads will be connection locations forthe electrochemically fabricated structure then the non-connection padsshould be protected from the electroless deposition. This may beaccomplished for example by the photoresist process set forth in theembodiment of FIGS. 5(a)-5(l). or by use of a contact mask (e.g. aconformable contact mask) or by use of other adhered masking techniques.

[0107] 3. As shown in FIG. 9(c), if desired or necessary (e.g., to avoiddamage to the wafer from plating or etching chemicals), enhance thepassivation layer of the IC by application of an additional passivationor a barrier layer 156 such as titanium nitride (TiN), tantalum (Ta),tantalum nitride (TaN), and/or polyimide. If the layer 156 isconductive, or if the contact pads on which connection between the waferand the electrochemically fabricated structure will be based areprotected (e.g., using the photoresist process set forth in theembodiment of FIGS. 5(a)-5(l)), then the passivation layer may beapplied prior to the operation leading to FIG. 9(b). As shown in FIG.9(d), a thin plating base of sacrificial material (here assumed to becopper) is deposited, e.g. by sputtering, over the entire surface of theintegrated circuit. In other embodiments deposition by directmetallization and associated plating may occur or by an electrolessprocess.

[0108] 4. Electrical contact is made to the thin copper and then thickcopper is electroplated as shown in FIG. 9(e).

[0109] 5. As shown in FIG. 9(f), the wafer is then planarized to revealflat nickel bumps surrounded by and co-planar with flat sacrificialcopper, thus forming a suitable substrate for electrochemicalfabrication. Prior to planarization, the wafer is fixtured if requiredsuch that its top surface and/or the top of bumps 152 are substantiallyplanar. The plane of planarization is chosen so as to remove the coatingof 156 (which may be insulating or of a material not desired in thefinal structure) from bumps 152. If some contact pads were protected bya nonconductive barrier, the nonconductive barrier may have been removedprior to the deposition of FIG. 9(c) or alternatively the protectioncould have remained place particularly if it was of a thickness thatpositioned its surface below that of the planarization level. In thesealternatives, the barrier may remain in place until structure formationis complete and the sacrificial material removed after which the barriermaterial may be removed.

[0110] 6. FIG. 9(g) shows a first layer consisting of structuralmaterial 162 (e.g., nickel) and sacrificial material 164 (e.g. copper)that have been formed using electrochemical fabrication techniques. Notethat at least one of the electrodeposited materials (as shown, thecopper) may need to ‘mushroom’ slightly over thin exposed edge 164 oflayer 156 if the latter is non-conductive.

[0111] 7. As shown in FIG. 9(h), successive layers are then formed overthe first layer via electrochemical fabrication techniques.

[0112] 8. FIG. 9(i) shows the resulting multi-layer IC-integratedstructure after the sacrificial material (e.g. copper) is etched withthe integrated circuit being protected by the deposited nickel and theoptionally applied layer 156.

[0113] 9. Finally, if layer 156 was applied and it is conductive, thenit must be removed (not shown), e.g., by wet or dry etching. If thebarrier was non-conductive it may remain assuming it isn't undesirablein the final device or that it isn't covering contact pads that areneeded for other operations. If the barrier layer is conductive andexists between the structural material (e.g. nickel) and the contactpads, reasonable control of the etching process will ensure that nosignificant damage to the interface occurs as the exposed portions ofthe barrier are removed.

[0114] A fourth group of embodiments may start off by protecting thecontact pads with a dielectric masking material, such as a contact maskor adhered mask. While the pads are protected, direct metallization andplating (e.g., using copper) of the surface of the passivation layer maybe performed. After this, a contact mask (if used) may be removed andthen structural material plated (e.g. nickel). The plating will coverthe contact pads once any dielectric gap between the surface of thepassivation layer and the contact pads is bridged by the mushroomingdeposition of structural material. If no gap exists, then plating to thepads will begin immediately along with the deposition over thepassivation layer.

[0115] One example embodiment from the fourth group of embodiments usesan adhered mask and is explained with the aid of FIGS. 10(a)-10(i). FIG.10(a) shows a wafer 102 ready to process. In FIG. 10(b), an adhered maskmaterial 166 has been applied and patterned. In FIG. 10(c), the waferhas been treated with a direct metallization treatment as is known tothe art (e.g., the shadow process from Electrochemicals USA) to formplatable layer 168. Alternatively, a platable layer can be applied usingan electroless process or using a sputtered or evaporated seed layer. InFIG. 10(d), a thick deposit of sacrificial material (e.g. copper) hasbeen deposited. In FIG. 10(e), wafer 102 has been planarized to exposemask material 166, allowing its removal as shown in FIG. 10(f). In FIG.10(g), structural material 172 (e.g., nickel) has started to be platedover the wafer (note that electrically isolated regions may not beplated or at least plated initially) beginning to ‘mushroom’ downtowards pads 140. Note that this assumes that passivation 112 representsa significant gap over which material 172 must ‘mushroom’. In FIG.10(h), material 172 has continued to be deposited, first mushrooming tocontact pads 140, then growing upwards from pads 140 which areconductive, until a thick layer has been deposited. FIG. 10(i) shows thewafer after planarization and ready to deposit the first layer in anelectrochemical fabrication process.

[0116] In some alternative embodiments, the direct metallization ordirect plating process may be replaced by a sputtering process, anelectroless deposition process, or the like. In some embodiments it maybe possible to use spray metal deposition to achieve an initial layer ofconductive material such as one of the processes described in U.S.Provisional Patent Application No. 60/435,324 described hereinelsewhere.

[0117] In other alternative embodiments, if necessary, some form ofintermediate coating may be applied between conductive pads on the IC(e.g. aluminum pads) and the metal (e.g. nickel) to be depositedthereon. Such coatings may include diffusion barrier materials (e.g.TiN, Ta, and/or TaN, and the like) and/or adhesion promoters (e.g. viaphosphoric acid anodizing, stannate immersion, zincate immersion, andthe like).

[0118] A fifth group of embodiments, illustrated in FIGS. 11(a)-11(k),allows structures produced using electrochemical fabrication to beanchored and mechanically secured to any region of wafer, whether pad orpassivation. FIG. 11(a) shows a wafer 102 ready for processing. Wafer102 may be coated with a passivation film (e.g., polyimide, not shown)into which apertures are formed corresponding to pads 140 which are tobe interfaced to the electrochemically-fabricated structure; this filmcan eventually be removed if desired.

[0119] In FIG. 11(b), a plating seed layer 174 (e.g., gold) has beenapplied to the surface of wafer 102. If necessary, adhesion layer 176(e.g., titanium or chromium) can be applied first (as is shown) toimprove adhesion of seed layer 174. If necessary, pads 140 can first becoated with a material that will protect them against the eventual etchof seed layer 174 and/or adhesion layer 176.

[0120] In FIG. 11(c), a patterned layer of masking material 178 (e.g.,photoresist) has been produced on wafer 102. In FIG. 11(d), structuralmaterial 180 (e.g., nickel) has been selectively deposited (e.g., byelectroplating) onto seed layer 174 and in FIG. 11(e), masking material178 has been removed. In FIG. 11(f), sacrificial material 182 (e.g.,copper) has been blanket-deposited (e.g., by electroplating) over wafer102. Both materials 180 and 182 are deposited in sufficient thickness toallow for subsequent planarization; FIG. 11(g) shows the result of thisplanarization step: the wafer is ready to deposit the first layer in anelectrochemical fabrication process.

[0121] In FIG. 11(h), multiple layers have been fabricated using anelectrochemical fabrication process, and in FIG. 11(i), after all layershave been formed, sacrificial material 182 has been removed (e.g., byetching). In FIG. 11(j), seed layer 174 and (if used) adhesion layer 176have been partially etched using a controlled etch so as to remove thesematerials other than where protected by overlying structural material176. In FIG. 11(k), bonding wires 184 have been attached to regions ofpads 140 that have no electrochemically-fabricated structure overlyingthem, if made large enough. In this way, some pads 140 can serve twopurposes: both to electrically connect the integrated device to theoutside world (through wire bonding as shown or flip chip (not shown),for example), and to electrically and mechanically connect to thestructure formed by electrochemical fabrication. Alternatively, somepads can be dedicated to forming off-chip electrical connections andsome dedicated to connecting to the electrochemically-fabricatedstructure, with interconnects between such pads provided belowpassivation layer 112 as required. According to this fifth group ofembodiments, structures produced by electrochemical fabrication may haveanchors to the wafer that partially or entirely overlap pads 140, or theanchors may be entirely decoupled from pads 140 and only anchored towafer passivation 112. Note that at least a portion of the function ofthe electrochemically-fabricated structure shown in FIG. 11 may be toredistribute the pads 140 into a new configuration, e.g., one moresuitable for interfacing the IC to the outside world.

[0122] Though the present embodiments have focused on electrochemicallyfabricated structures containing a structural material of nickel and asacrificial material of copper, other embodiments are possible wheredifferent structural and/or sacrificial materials are used. Furthermore,interfacing between a wafer or die and electrochemically producedstructures utilizing different structural and/or sacrificial materialsmay occur via the nickel and copper materials exemplified herein or mayoccur via the different materials according to the generalizedapplicability of the processes set forth herein to those materials.Still other embodiments will be apparent to those of skill in the artupon reviewing the teaching herein, such as processes that involvesvarious combinations of the operations used in the different embodimentsdisclosed herein.

[0123] Various alternatives to and variations of the above notedembodiments exist. In some alternative embodiments, the structuralmaterial of choice is nickel and the sacrificial material of choice iscopper, and in other embodiments other or additional structuralmaterials may be chosen and other or additional sacrificial materialsmay be chosen.

[0124] The patent applications and patents set forth below are herebyincorporated by reference herein as if set forth in full. The gist ofeach patent application or patent is included in the table to aid thereader in finding specific types of teachings. It is not intended thatthe incorporation of subject matter be limited to those topicsspecifically indicated, but instead the incorporation is to include allsubject matter found in these applications. The teachings in theseincorporated applications can be combined with the teachings of theinstant application in many ways: For example, enhanced methods ofproducing structures may be derived from the combination of teachings,enhanced structures may be obtainable, enhanced apparatus may bederived, and the like.

[0125] U.S. patent application Ser. No. 09/488,142, filed Jan. 20, 2000,and entitled “An Apparatus for Electrochemical Fabrication Comprising AConformable Mask” is a divisional of the application that led to theabove noted '630 patent. This application describes the basics ofconformable contact mask plating and electrochemical fabricationincluding various alternative methods and apparatus for practicing EFABas well as various methods and apparatus for constructing conformablecontact masks.

[0126] U.S. patent application Ser. No. 60/415,374, filed on Oct. 1,2002, and and entitled “Monolithic Structures Including Alignment and/orRetention Fixtures for Accepting Components” is generally directed to apermanent or temporary alignment and/or retention structures forreceiving multiple components are provided. The structures arepreferably formed monolithically via a plurality of depositionoperations (e.g. electrodeposition operations). The structures typicallyinclude two or more positioning fixtures that control or aid in thepositioning of components relative to one another, such features mayinclude (1) positioning guides or stops that fix or at least partiallylimit the positioning of components in one or more orientations ordirections, (2) retention elements that hold positioned components indesired orientations or locations, and (3) positioning and/or retentionelements that receive and hold adjustment modules into which componentscan be fixed and which in turn can be used for fine adjustments ofposition and/or orientation of the components.

[0127] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US026-A-MG), filed on Apr. 21, 2003, and entitled“Methods of Reducing Discontinuities Between Layers of ElectrochemicallyFabricated Structures” is generally directed to various embodimentsproviding electrochemical fabrication methods and apparatus for theproduction of three-dimensional structures from a plurality of adheredlayers of material including operations or structures for reducingdiscontinuities in the transitions between adjacent layers. Someembodiments improve the conformance between a size of producedstructures (especially in the transition regions associated with layershaving offset edges) and the intended size of the structure as derivedfrom original data representing the three-dimensional structures. Someembodiments make use of selective and/or blanket chemical and/orelectrochemical deposition processes, selective and or blanket chemicaland/or electrochemical etching process, or combinations thereof. Someembodiments make use of multi-step deposition or etching operationsduring the formation of single layers.

[0128] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US029-A-MG), filed on May 7, 2003, and entitled“EFAB With Selective Transfer Via Instant Mask” is generally directed tothree-dimensional structures that are electrochemically fabricated bydepositing a first material onto previously deposited material throughvoids in a patterned mask where the patterned mask is at leasttemporarily adhered to a substrate or previously formed layer ofmaterial and is formed and patterned onto the substrate via a transfertool patterned to enable transfer of a desired pattern of precursormasking material. In some embodiments the precursor material istransformed into masking material after transfer to the substrate whilein other embodiments the precursor is transformed during or beforetransfer. In some embodiments layers are formed one on top of another tobuild up multi-layer structures. In some embodiments the mask materialacts as a build material while in other embodiments the mask material isreplaced each layer by a different material which may, for example, beconductive or dielectric.

[0129] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US030-A-MG), filed on May 7, 2003, and entitled“Three-Dimensional Object Formation Via Selective lnkjet Printing &Electrodeposition” is generally directed to three-dimensional structuresthat are electrochemically fabricated by depositing a first materialonto previously deposited material through voids in a patterned maskwhere the patterned mask is at least temporarily adhered to previouslydeposited material and is formed and patterned directly from materialselectively dispensed from a computer controlled dispensing device (e.g.an ink jet nozzle or array or an extrusion device). In some embodimentslayers are formed one on top of another to build up multi-layerstructures. In some embodiments the mask material acts as a buildmaterial while in other embodiments the mask material is replaced eachlayer by a different material which may, for example, be conductive ordielectric.

[0130] U.S. patent application Ser. No. 10/271,574, filed on Oct. 15,2002, and entitled “Methods of and Apparatus for Making High AspectRatio Microelectromechanical Structures” is generally directed tovarious embodiments of the invention presenting techniques for formingstructures (e.g. HARMS-type structures) via an electrochemical extrusion(ELEX™) process. Preferred embodiments perform the extrusion processesvia depositions through anodeless conformable contact masks that areinitially pressed against substrates that are then progressively pulledaway or separated as the depositions thicken. A pattern of depositionmay vary over the course of deposition by including more complexrelative motion between the mask and the substrate elements. Suchcomplex motion may include rotational components or translationalmotions having components that are not parallel to an axis ofseparation. More complex structures may be formed by combining the ELEX™process with the selective deposition, blanket deposition,planarization, etching, and multi-layer operations of EFAB™.

[0131] U.S. patent application Ser. No. 60/435,324, filed on Dec. 20,2002, and entitled “EFAB Methods and Apparatus Including Spray Metal orPowder Coating Processes”, is generally directed to various embodimentsof the invention presenting techniques for forming structures via acombined electrochemical fabrication process and a thermal sprayingprocess. In a first set of embodiments, selective deposition occurs viaconformable contact masking processes and thermal spraying is used inblanket deposition processes to fill in voids left by selectivedeposition processes. In a second set of embodiments, selectivedeposition via a conformable contact masking is used to lay down a firstmaterial in a pattern that is similar to a net pattern that is to beoccupied by a sprayed metal. In these other embodiments a secondmaterial is blanket deposited to fill in the voids left in the firstpattern, the two depositions are planarized to a common level that maybe somewhat greater than a desired layer thickness, the first materialis removed (e.g. by etching), and a third material is sprayed into thevoids left by the etching operation. The resulting depositions in boththe first and second sets of embodiments are planarized to a desiredlayer thickness in preparation for adding additional layers to formthree-dimensional structures from a plurality of adhered layers. Inother embodiments, additional materials may be used and differentprocesses may be used.

[0132] U.S. patent application Ser. No. 60/429,483, filed on Nov. 26,2002, and entitled “Multi-cell Masks and Methods and Apparatus for UsingSuch Masks to Form Three-Dimensional Structures” is generally directedto multilayer structures that are electrochemically fabricated viadepositions of one or more materials in a plurality of overlaying andadhered layers. Selectivity of deposition is obtained via a multi-cellcontrollable mask. Alternatively, net selective deposition is obtainedvia a blanket deposition and a selective removal of material via amulti-cell mask. Individual cells of the mask may contain electrodescomprising depositable material or electrodes capable of receivingetched material from a substrate. Alternatively, individual cells mayinclude passages that allow or inhibit ion flow between a substrate andan external electrode and that include electrodes or other controlelements that can be used to selectively allow or inhibit ion flow andthus inhibit significant deposition or etching.

[0133] U.S. patent application Ser. No. 60/429,484, filed on Nov. 26,2002, and entitled “Non-Conformable Masks and Methods and Apparatus forForming Three-Dimensional Structures” is generally directed toelectrochemical fabrication used to form multilayer structures (e.g.devices) from a plurality of overlaying and adhered layers. Masks, thatare independent of a substrate to be operated on, are generally used toachieve selective patterning. These masks may allow selective depositionof material onto the substrate or they may allow selective etching of asubstrate where after the created voids may be filled with a selectedmaterial that may be planarized to yield in effect a selectivedeposition of the selected material. The mask may be used in a contactmode or in a proximity mode. In the contact mode the mask and substratephysically mate to form substantially independent process pockets. Inthe proximity mode, the mask and substrate are positioned sufficientlyclose to allow formation of reasonably independent process pockets. Insome embodiments, masks may have conformable contact surfaces (i.e.surfaces with sufficient deformability that they can substantiallyconform to surface of the substrate to form a seal with it) or they mayhave semi-rigid or even rigid surfaces. Post deposition etchingoperations may be performed to remove flash deposits (thin undesireddeposits).

[0134] U.S. patent application Ser. No. 10/309,521, filed on Dec. 3,2002, and entitled “Miniature RF and Microwave Components and Methodsfor Fabricating Such Components” is generally directed to RF andmicrowave radiation directing or controlling components provided thatmay be monolithic, that may be formed from a plurality ofelectrodeposition operations and/or from a plurality of deposited layersof material, that may include switches, inductors, antennae,transmission lines, filters, and/or other active or passive components.Components may include non-radiation-entry and non-radiation-exitchannels that are useful in separating sacrificial materials fromstructural materials. Preferred formation processes use electrochemicalfabrication techniques (e.g. including selective depositions, bulkdepositions, etching operations and planarization operations) andpost-deposition processes (e.g. selective etching operations and/or backfilling operations).

[0135] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US049-A-MG), filed on May 7, 2003, and entitled“Method for Fabricating Three-Dimensional Structures Including SurfaceTreatment of a First Material in Preparation for Deposition of a SecondMaterial” is generally directed to a method of fabricatingthree-dimensional structures from a plurality of adhered layers of atleast a first and a second material wherein the first material is aconductive material and wherein each of a plurality of layers includestreating a surface of a first material prior to deposition of the secondmaterial. The treatment of the surface of the first material either (1)decreases the susceptibility of deposition of the second material ontothe surface of the first material or (2) eases or quickens the removalof any second material deposited on the treated surface of the firstmaterial In some embodiments the treatment of the first surface includesforming a dielectric coating over the surface while the deposition ofthe second material occurs by an electrodeposition process (e.g. anelectroplating or electrophoretic process).

[0136] U.S. patent application Ser. No. 10/387,958, filed on Mar. 13,2003, and entitled “Electrochemical Fabrication Method and Apparatus forProducing Three-Dimensional Structures Having Improved Surface Finish”is generally directed to an electrochemical fabrication process thatproduces three-dimensional structures (e.g. components or devices) froma plurality of layers of deposited materials wherein the formation of atleast some portions of some layers are produced by operations thatremove material or condition selected surfaces of a deposited material.In some embodiments, removal or conditioning operations are variedbetween layers or between different portions of a layer such thatdifferent surface qualities are obtained. In other embodiments varyingsurface quality may be obtained without varying removal or conditioningoperations but instead by relying on differential interaction betweenremoval or conditioning operations and different materials encounteredby these operations.

[0137] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US057-A-SC), filed on May 7, 2003, and entitled“Methods and Apparatus for Monitoring Deposition Quality DuringConformable Contact Mask Plating Operations” is generally directed to aelectrochemical fabrication (e.g. EFAB) processes and apparatus aredisclosed that provide monitoring of at least one electrical parameter(e.g. voltage) during selective deposition where the monitored parameteris used to help determine the quality of the deposition that was made.If the monitored parameter indicates that a problem occurred with thedeposition, various remedial operations may be undertaken to allowsuccessful formation of the structure to be completed.

[0138] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US059-A-SC), filed on May 7, 2003, and entitled“Conformable Contact Masking Methods and Apparatus Utilizing In SituCathodic Activation of a Substrate” is generally directed to aelectroplating processes (e.g. conformable contact mask plating andelectrochemical fabrication processes) that includes in situ activationof a surface onto which a deposit will be made are described. At leastone material to be deposited has an effective deposition voltage that ishigher than an open circuit voltage, and wherein a deposition controlparameter is capable of being set to such a value that a voltage can becontrolled to a value between the effective deposition voltage and theopen circuit voltage such that no significant deposition occurs but suchthat surface activation of at least a portion of the substrate canoccur. After making electrical contact between an anode, that comprisesthe at least one material, and the substrate via a plating solution,applying a voltage or current to activate the surface without anysignificant deposition occurring, and thereafter without breaking theelectrical contact, causing deposition to occur.

[0139] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US060-A-SC), filed on May 7, 2003, and entitled“Electrochemical Fabrication Methods With Enhanced Post DepositionProcessing” is generally directed to a electrochemical fabricationprocess for producing three-dimensional structures from a plurality ofadhered layers is provided where each layer comprises at least onestructural material (e.g. nickel) and at least one sacrificial material(e.g. copper) that will be etched away from the structural materialafter the formation of all layers have been completed. A copper etchantcontaining chlorite (e.g. Enthone C-38) is combined with a corrosioninhibitor (e.g. sodium nitrate) to prevent pitting of the structuralmaterial during removal of the sacrificial material. A simple processfor drying the etched structure without the drying process causingsurfaces to stick together includes immersion of the structure in waterafter etching and then immersion in alcohol and then placing thestructure in an oven for drying.

[0140] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US064-A-MG), filed on May 7, 2003, and entitled∓Methods of and Apparatus for Molding Structures Using Sacrificial MetalPatterns” is generally directed to molded structures, methods of andapparatus for producing the molded structures. At least a portion of thesurface features for the molds are formed from multilayerelectrochemically fabricated structures (e.g. fabricated by the EFAB™formation process), and typically contain features having resolutionswithin the 1 to 100 μm range. The layered structure is combined withother mold components, as necessary, and a molding material is injectedinto the mold and hardened. The layered structure is removed (e.g. byetching) along with any other mold components to yield the moldedarticle. In some embodiments portions of the layered structure remain inthe molded article and in other embodiments an additional moldingmaterial is added after a partial or complete removal of the layeredstructure.

[0141] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US065-A-MG), filed on May 7, 2003, and entitled“Electrochemically Fabricated Structures Having Dielectric or ActiveBases and Methods of and Apparatus for Producing Such Structures” isgenerally directed to multilayer structures that are electrochemicallyfabricated on a temporary (e.g. conductive) substrate and are thereafterbonded to a permanent (e.g. dielectric, patterned, multi-material, orotherwise functional) substrate and removed from the temporarysubstrate. In some embodiments, the structures are formed from top layerto bottom layer, such that the bottom layer of the structure becomesadhered to the permanent substrate, while in other embodiments thestructures are form from bottom layer to top layer and then a doublesubstrate swap occurs. The permanent substrate may be a solid that isbonded (e.g. by an adhesive) to the layered structure or it may startout as a flowable material that is solidified adjacent to or partiallysurrounding a portion of the structure with bonding occurs duringsolidification. The multilayer structure may be released from asacrificial material prior to attaching the permanent substrate or itmay be released after attachment.

[0142] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US066-A-MG), filed on May 7, 2003, and entitled“Electrochemically Fabricated Hermetically Sealed Microstructures andMethods of and Apparatus for Producing Such Structures” is generallydirected to multilayer structures that are electrochemically fabricatedfrom at least one structural material (e.g. nickel), at least onesacrificial material (e.g. copper), and at least one sealing material(e.g. solder). In some embodiments, the layered structure is made tohave a desired configuration which is at least partially and immediatelysurrounded by sacrificial material which is in turn surrounded almostentirely by structural material. The surrounding structural materialincludes openings in the surface through which etchant can attack andremove trapped sacrificial material found within. Sealing material islocated near the openings. After removal of the sacrificial material,the box is evacuated or filled with a desired gas or liquid. Thereafter,the sealing material is made to flow, seal the openings, and resolidify.In other embodiments, a post-layer formation lid or other enclosurecompleting structure is added.

[0143] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US067-A-MG), filed on May 7, 2003, and entitled“Multistep Release Method for Electrochemically Fabricated Structures”is generally directed to multilayer structures that areelectrochemically fabricated from at least one structural material (e.g.nickel), that is configured to define a desired structure and which maybe attached to a substrate, and from at least one sacrificial material(e.g. copper) that surrounds the desired structure. After structureformation, the sacrificial material is removed by a multi-stage etchingoperation. In some embodiments sacrificial material to be removed may belocated within passages or the like on a substrate or within an add-oncomponent. The multi-stage etching operations may be separated byintermediate post processing activities, they may be separated bycleaning operations, or barrier material removal operations, or thelike. Barriers may be fixed in position by contact with structuralmaterial or with a substrate or they may be solely fixed in position bysacrificial material and are thus free to be removed after all retainingsacrificial material is etched.

[0144] U.S. patent application Ser. No. XX/XXX,XXX, (Corresponding toMEMGen Docket No. P-US068-A-MG), filed on May 7, 2003, and entitled“Methods of and Apparatus for Electrochemically Fabricating StructuresVia Interlaced Layers or Via Selective Etching and Filling of Voids” isgenerally directed to multi-layer structures that are electrochemicallyfabricated by depositing a first material, selectively etching the firstmaterial (e.g. via a mask), depositing a second material to fill in thevoids created by the etching, and then planarizing the depositions so asto bound the layer being created and thereafter adding additional layersto previously formed layers. The first and second depositions may be ofthe blanket or selective type. The repetition of the formation processfor forming successive layers may be repeated with or without variations(e.g. variations in: patterns; numbers or existence of or parametersassociated with depositions, etchings, and or planarization operations;the order of operations, or the materials deposited). Other embodimentsform multi-layer structures using operations that interlace materialdeposited in association with some layers with material deposited inassociation with other layers.

[0145] Various other embodiments exist. Some of these embodiments may bebased on a combination of the teachings herein with various teachingsincorporated herein by reference. Some embodiments may not use anyblanket deposition process and/or they may not use a planarizationprocess. Some embodiments may involve the selective deposition of aplurality of different materials on a single layer or on differentlayers. Some embodiments may use blanket depositions processes that arenot electrodeposition processes. Some embodiments may use selectivedeposition processes on some layers that are not conformable contactmasking processes and are not even electrodeposition processes. Someembodiments may use nickel as a structural material while otherembodiments may use different materials such as gold, silver, or anyother electrodepositable materials that can be separated from the copperand/or some other sacrificial material. Some embodiments may use copperas the structural material with or without a sacrificial material. Someembodiments may remove a sacrificial material while other embodimentsmay not. In some embodiments the anode may be different from theconformable contact mask support and the support may be a porousstructure or other perforated structure. Some embodiments may usemultiple conformable contact masks with different patterns so as todeposit different selective patterns of material on different layersand/or on different portions of a single layer. In some embodiments, thedepth of deposition will be enhanced by pulling the conformable contactmask away from the substrate as deposition is occurring in a manner thatallows the seal between the conformable portion of the CC mask and thesubstrate to shift from the face of the conformal material to the insideedges of the conformable material.

[0146] In view of the teachings herein, many further embodiments,alternatives in design and uses of the invention will be apparent tothose of skill in the art. As such, it is not intended that theinvention be limited to the particular illustrative embodiments,alternatives, and uses described above but instead that it be solelylimited by the claims presented hereafter.

We claim:
 1. An electrochemical fabrication process for producing athree-dimensional structure from a plurality of adhered layers, theprocess comprising: (A) selectively depositing at least a portion of alayer onto the substrate, wherein the substrate may comprise previouslydeposited material; (B) forming a plurality of layers such thatsuccessive layers are formed adjacent to and adhered to previouslydeposited layers, wherein said forming comprises repeating operation (A)a plurality of times; wherein at least a plurality of the selectivedepositing operations comprise: (1) locating a mask on or in proximityto a substrate; (2) in presence of a plating solution, conducting anelectric current between an anode and the substrate through the at leastone opening in the mask, such that a selected deposition material isdeposited onto the substrate to form at least a portion of a layer; and(3) separating the selected preformed mask from the substrate; whereinthe substrate comprises a semiconductor wafer or single die containingelectrical circuitry and having contact pads to which structuralmaterial is to connect; and wherein the process of contacting thecontact pads with structural material comprises treating the wafer ordie with a transition treatment and then applying a structural materialto the contact pads by application of an electroless plating solution tothe contact pads for a sufficient time to form a deposition of desiredthickness.
 2. The process of claim 1, wherein a plurality of layerscomprise at least one structural material and at least one sacrificialmaterial.
 3. The process of claim 1 additionally comprising: (A)supplying a plurality of preformed masks, wherein each mask comprises apatterned dielectric material that includes at least one opening throughwhich deposition can take place during the formation of at least aportion of a layer, and wherein each mask comprises a support structurethat supports the patterned dielectric material; and wherein thelocating of a mask on or in proximity to a substrate comprisescontacting the substrate and the dielectric material of a selectedpreformed mask.
 4. The process of claim 1 wherein the locating of a maskon or in proximity to a substrate comprises forming and adhering apatterned mask to the substrate.
 5. The process of claim 1 wherein afterapplication of structural material to the contact pads, a layer ofsacrificial material is applied to the surface of the wafer or die. 6.The process of claim 1 wherein the applied layer of sacrificial materialhas a thickness less than a desired thickness and is increased to adesired thickness by electroplating.
 7. The process of claim 5 whereinafter application of the sacrificial material, the deposited sacrificialand structural materials are planarized to yield a substrate comprisingselective regions of sacrificial and structural material deposition onto which additional layers of a structural material and a sacrificialmaterial will be deposited.
 8. The process of claim 1 wherein theprocess further comprises applying a transition treatment to the contactpads.
 9. The process of claim 8 wherein transition treatment comprisesapplication of an adhesion promoter.
 10. The process of claim 8 whereintransition treatment comprises application of a diffusion barrier. 11.The process of claim 1 wherein the structural material comprises nickel.12. The process of claim 1 wherein the sacrificial material comprisecopper.
 13. An electrochemical fabrication process for producing athree-dimensional structure from a plurality of adhered layers, theprocess comprising: (A) selectively depositing at least a portion of alayer onto the substrate, wherein the substrate may comprise previouslydeposited material; (B) forming a plurality of layers such thatsuccessive layers are formed adjacent to and adhered to previouslydeposited layers, wherein said forming comprises repeating operation (A)a plurality of times; wherein at least a plurality of the selectivedepositing operations comprise: (1) locating a mask on or in proximityto a substrate; (2) in presence of a plating solution, conducting anelectric current between an anode and the substrate through the at leastone opening in the mask, such that a selected deposition material isdeposited onto the substrate to form at least a portion of a layer; and(3) separating the selected preformed mask from the substrate; whereinthe substrate comprises a semiconductor wafer or single die containingelectrical circuitry and having contact pads to which structuralmaterial is to connect; and wherein the process of forming a conductivelayer over a surface of the wafer or die comprises: (a) shielding atleast the contact pads with a shielding material; (b) depositing asacrificial material to unshielded regions using at least one of directmetallization or direct plating or electroless deposition; (c) removingthe shielding after a deposition of the sacrificial material; and (d)depositing a structural material to the contact pads.
 14. The process ofclaim 13, wherein a plurality of layers comprise at least one structuralmaterial and at least one sacrificial material.
 15. The process of claim13 additionally comprising: (A) supplying a plurality of preformedmasks, wherein each mask comprises a patterned dielectric material thatincludes at least one opening through which deposition can take placeduring the formation of at least a portion of a layer, and wherein eachmask comprises a support structure that supports the patterneddielectric material; and wherein the locating of a mask on or inproximity to a substrate comprises contacting the substrate and thedielectric material of a selected preformed mask.
 16. The process ofclaim 13 wherein the locating of a mask on or in proximity to asubstrate comprises forming and adhering a patterned mask to thesubstrate.
 17. The process of claim 13 wherein after deposition of thesacrificial material and removal of the shielding, applying a treatmentto the contact pads prior to depositing the structural material.
 18. Theprocess of claim 17 wherein the treatment comprises a treatment thatenhances adhesion between the structural material and the contact pad.19. The process of claim 13 wherein the deposition of the structuralmaterial comprises electroplating the structural material onto at leastone contact pads via deposition of structural material onto thesacrificial material wherein the region of deposition of the structuralmaterial expands to bridge a dielectric gap separating the sacrificialmaterial from the at least one contact pad.
 20. The process of claim 18wherein after deposition of the structural material, the depositedsacrificial and structural materials are planarized to yield a substratecomprising selective regions of sacrificial and structural materialdeposition on to which one or more layers comprising a structuralmaterial and a sacrificial material will be deposited.
 21. The processof claim 13 wherein the process further comprises applying a transitiontreatment to the contact pads.
 22. The process of claim 21 whereintransition treatment comprises application of an adhesion promoter. 23.The process of claim 21 wherein transition treatment comprisesapplication of a diffusion barrier.
 24. The process of claim 13 whereinthe structural material comprises nickel.
 25. The process of claim 13wherein the sacrificial material comprise copper.
 26. An electrochemicalfabrication process for producing a three-dimensional structure from aplurality of adhered layers, the process comprising: (A) selectivelydepositing at least a portion of a layer onto the substrate, wherein thesubstrate may comprise previously deposited material; (B) forming aplurality of layers such that successive layers are formed adjacent toand adhered to previously deposited layers, wherein said formingcomprises repeating operation (A) a plurality of times; wherein at leasta plurality of the selective depositing operations comprise: (1)locating a mask on or in proximity to a substrate; (2) in presence of aplating solution, conducting an electric current between an anode andthe substrate through the at least one opening in the mask, such that aselected deposition material is deposited onto the substrate to form atleast a portion of a layer; and (3) separating the selected preformedmask from the substrate; wherein the substrate comprises a semiconductorwafer or single die containing electrical circuitry and having contactpads to which structural material is to connect and having regions ofdielectric where structural material is to adhere; and wherein theprocess of contacting the structural material to regions of dielectricmaterial comprises depositing a conductive base material, in a patternedor unpatterned formation, depositing structural material to at leastselected locations of the base material and, if base material exists inany regions which are not overlaid by structural material, subsequentlyremoving any such base material that is not overlaid.